1. Field
This disclosure relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in personal navigation devices, cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate and channel regions are positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique for Non-Volatile Memory;” U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” and U.S. Pat. No. 6,888,758, titled “Programming Non-Volatile Memory,” all three cited patents are incorporated herein by reference in their entirety.
In many cases, the program voltage is applied to the control gate as a series of pulses (referred to as programming pulses), with the magnitude of the pulses increasing at each pulse. Between programming pulses, a set of one or more verify operations are performed to determine whether the memory cell(s) being programmed have reached their target level. If a memory cell has reached its target level, programming stops for that memory cell. If a memory cell has not reached its target level, programming will continue for that memory cell.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary memory device.
A multi-state memory device stores multiple bits of data per memory cell by identifying multiple distinct valid threshold voltage (Vt) distributions (or data states). Each distinct Vt distribution corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, a memory cell that stores two bits of data uses four valid Vt distributions. A memory cell that stores three bits of data uses eight valid Vt distributions.
Once a non-volatile storage element has been programmed, it is important that its programming state can be read back with a high degree of reliability. However, the sensed programming state can sometimes vary from the intended programming state due to factors including noise and the tendency of devices to gravitate towards charge neutrality over time.
Consequently, it is possible to encounter erroneous or corrupted data bits at the time of reading non-volatile memory. Typically, some form of error checking and correction algorithm (“correction algorithm”) is applied to check for and correct any corrupted data bits. One correction algorithm stores additional parity bits to set the parity of a group of data bits to a required logical level during the write process. The additional parity bits are sometimes referred to as an Error Correction Code (ECC). During the read process, the correction algorithm decodes the bits by computing the parity of the group of data bits to detect any corrupted data. The correction algorithm corrects data that is not too severely corrupted. However, if the data is too severely corrupted the ECC code may not be able to correct the data.